Accès direct au contenu


Sébastien Pillement Research

A- A+ Aa

Research activities

Abstract of my activities

The research that I address focuses on the design of dynamically reconfigurable systems. Constant evolution of applications and the ever-increasing need for performances require the development of new efficient and flexible architectures. These constraints have led to more complex architectures, their reconfiguration mechanisms and management.

Low-Power and reliable dynamically reconfigurable architecture

In this theme we intend to define new embedded architectures. In the first part of my work, we propose architectures providing a good compromise between performance, power consumption, and flexibility. My research addressed the issue of creating a flexible platform with the greatest efficiency possible.The modern SoCs include a large number of heterogeneous features, and face problems due to technology shrink. The main issue of this axis is the need to develop fault-tolerant systems. This property needs to be adressed at the architectural level by defining new structure but also by providing reliable interconnection infrastructures (such as Network-on-Chip). We are studying new coding and new technologies to reduce consumption of interconnect while improving their reliability. We are also working to define flexible networks adapted to the dynamic reconfiguration paradigm.

Methods and system management

In this axis, I am working on the development of tools and methods suitable for reconfigurable embedded systems. The emergence of reconfigurable systems requires the use of specific tools and mechanisms. In particular, the presence of a dedicated operating system becomes necessary. I am particularly interested in the definition of management services architectures including placement and task scheduling aspects inside a reconfigurable System-on-Chip (RSoC). The establishment of specific management can develop reliable dynamically reconfigurable systems, we then propose OS services in that sense. And finally, the design framework should take into account this new optimisation constraint in order to increase the reliability of the architecture (design for reliability).


International Collaborations

  • University of Erlangen-Nuremberg (Germany): Co-design Of Massively Parallel Embedded Processore Architectures.
  • University of Karlsruhe (Germany): Design of virtualization layer for heterogeneous many-core architectures.
  • TU Eindhoven (Netherland): Communication infrastructure and dynamic management.

National Collaborations

  • University of Bretagne Occidentale, Lab-STICC.
  • University of Rennes 1, IRISA.
  • University of Lorraine, IJL.
  • University of Nantes, LS2N.

Industrial Collaborations

  • Thales Research and Technologies, Palaiseau.
  • ATMEL SAS, Nantes.
  • INTEL, Nantes.
  • STMicroelectronics, Le Mans.
  • CEA, Palaiseau.


  • 2015-2019: Holistic Approach for Reliability (HoliStar) CEATech project.
  • 2015-2018: Safe and ProgrAmmable Real-Time Embedded Systems (SPARTE) RFI region project.
  • 2014-2018: Reliasic Brittany region and CominLab project. Designing reliable applications on unreliable architectures.
  • 2011-2014: FlexTiles project. European FP7 Project
  • 2011-2015: ARDyT Architecture Reconfigurable Dynamiquement Tolérante aux fautes. ANR INS (Ingénierie Numérique et Sécurité) Project
  • 2010-2012: ARF project Architecture Reconfigurable Fiable. Défis scientifiques émergents de l'Université de Rennes 1
  • 2008-2011: FosFor (Flexible Operating System FOr Reconfigurable platform) ANR ARFU (Architectures du Futur) Project
  • 2008-2011: CIFAER (Communications Intra-véhicule et Architecture Embarquée Reconfigurable) ANR ARFU (Architectures du Futur) Project


Current Ph.D. students

  • Simei Yang (2016-2019): Evaluation and design of run-time managers for Ultra-Low Power MPSoC
  • Tien Thanh Nguyen (2016-2019): Fault mitigation techniques for heterogeneous MPSoC design
  • Dimitry Solet (2015-2018): SPARTES : Safe and ProgrAmmable Real – Time Embedded Systems

Ph.D. Graduates

Master students

  • Meng Zhang (2013): Fault-Tolerant reconfigurable hardware basic block .
    Master of research 'SEGE' of University of Nantes.
  • Shaoyang Men (2013): Distributed spectrum sensing in cognitive wireless sensor networks.
    Master of research 'SEGE' of University of Nantes.
  • Le Quang Hoa (2012): Implementation of Pfair for Dynamically reconfigurable architectures.
    Master of research 'SISEA' of University of Rennes 1.
  • Surya Narayanan (2011): Communication Service and Dynamic Memory Management for hardware tasks executed on Dynamic and Partial Reconfigurable resources.
    Master of Science in 'Computer engineering' of TU Delft.
  • Thibault Brier (2011): Energy optimization of the DRAFT Network On Chip.
    Master of research 'SISEA' of University of Rennes 1.
  • Adnan Akhtar (2010): Model Simulation and Verification of Dynamically Reconfigurable MPSoC.
    Master research in 'System on Chip Design' of Royal Institute of Technology (KTH).
  • Syed Jafri (2009): Fault Tolerance in Reconfigurable Embedded Systems.
    Master research in 'System on Chip Design' of Royal Institute of Technology (KTH).
  • Sana Ben Sassi (2009): Estimation des performances des réseaux d’interconnexion flexibles.
    Master research in 'System on Chip' of National Engineering Institute of Sousse.


A comprehensive presentation of our research activities for the design of reliable and reconfigurable architectures is here