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Sébastien Pillement Research

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Full list of publications. Sorted by year.

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Recent Publications


Articles

[2021] 0-1 ILP-based Run-Time Hierarchical Energy Optimization for Heterogeneous Cluster-based multi/many-core Systems (S. Yang, S. Le Nours, M. Mendez-Real, S. Pillement), In Journal of System Architecture, 2021. [bib] [doi]
[2021] A Measurement-based Message-level Timing Prediction Approach for Data-Dependent SDFGs on Tile-based Heterogeneous MPSoCs (R. Stemmer, H. Vu, S. Le Nours, K. Grüttner, S. Pillement, W. Nebel), In Applied Sciences (Switzerland), 2021. [bib]
[2020] Energy-efficient GPS synchronization for wireless nodes (D. Pallier, V. Le Cam, S. Pillement), In IEEE Sensors Journal, volume 21, 2020. [bib] [doi]
[2017] FTUC: A Flooding Tree Uneven Clustering protocol for wireless sensor network (H. Wei, S. Pillement, D. Xu), In SENSORS, volume 17, 2017. [bib] [doi]
[2017] Cooperative Spectrum Sensing With Small Sample Size in CWSNs (S. Men, P. Chargé, S. Pillement), In Wireless Personal Communications, volume 96, 2017. [bib] [doi]

International Conference Papers

[2021] Experimental Evaluation of Statistical Model Checking Methods for Probabilistic Timing Analysis of Multiprocessor Systems (H. Vu, S. Le Nours, S. Pillement), In Euromicro Digital System Design (DSD), 2021. [bib]
[2021] A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoC (H. Vu, S. Le Nours, S. Pillement, R. Stemmer, K. Gruettner), In ASP-DAC, 2021. [bib]
[2020] SPEAR: Hardware-based Implicit Rewriting for Square-root Verification (A. Yasin, T. Su, S. Pillement, M. Cieselski), In Design Automation and Test in Europe, 2020. [bib]
[2020] Formal Verification of Constrained Arithmetic Circuits Using Computer Algebraic Approach (T. Su, A. Yasin, S. Pillement, M. Cieselski), In Symposium on VLSI (ISVLSI), 2020. [bib]
[2020] Towards Probabilistic Timing Analysis for SDFGs on Tile Based Heterogeneous MPSoCs (R. Stemmer, H. Vu, S. Pillement, S. Le Nours, K. Gruttner), In Embedded Real Time Systems (ERTS), 2020. [bib]
[2020] Towards Malicious Exploitation of Energy Management Mechanisms (S. Noubir, M. M. Real, S. Pillement), In Design Automation and Test in Europe, 2020. [bib]
[2019] Functional Verification of Hardware Dividers using Algebraic Model (A. Yasin, T. Su, S. Pillement, M. Cieselski), In Conference on Very Large Scale Integration (VLSI-SoC), 2019. [bib]
[2019] Formal Verification of Integer Dividers: Division by a Constant (A. Yasin, T. Su, S. Pillement, M. Cieselski), In ISVLSI Symposium, 2019. [bib]
[2019] Mapping and Frequency Joint Optimization for Energy Efficient Execution of Multiple Applications on Multicore Systems (Yang S., M. M. Real, S. Le Nours, S. Pillement), In DASIP, 2019. [bib]
[2019] System-Level Modeling and Simulation of MPSoC Run-Time Management using Execution Traces Analysis (S. Yang, S. Le Nours, M. Mendez Real, S. Pillement), In Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIX), 2019. [bib]
[2019] Experimental Evaluation of Probabilistic Execution-Time Modeling and Analysis Methods for SDF Applications on MPSoCs. (R. Stemmer, H.D. Vu, K. Gruttner, S. Le Nours, W. Nebel, S. Pillement), In Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIX), 2019. [bib]
[2018] Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection (D. Solet, M. Briday, J.L. Bechennec, S. Faucou, S. Pillement), In European Dependable Computing Conference, 2018. [bib]
[2018] HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems (D. Solet, M. Briday, J.L. Bechennec, S. Faucou, S. Pillement), In NASA/ESA Conference on Adaptive Hardware and Systems, 2018. [bib]
[2018] FPGA Side Channel Attacks without Physical Access (C. Ramesh, S. Patil, S.Nishok Dhanuskodi, G. Provelengios, S. Pillement, D. Holcomb, R. Tessier), In International Symposium on Field-Programmable Custom Computing Machines, 2018. [bib]
[2017] Model-driven reliability evaluation for MPSoC design (TT Nguyen, A. Mouraud, M. Thévenin, G. Corre, O. Pasquier, S. Pillement), In DASIP, 2017. [bib]
[2016] Hardware Runtime Verification of Embedded Software in SoPC (D. Solet, and J.L. Bechennec, M. Briday, S. Faucou, S. Pillement), In International Symposium on Industrial Embedded Systems, 2016. [bib]

International Workshop Papers

[2019] Offset Tracking of sensor clock using Kalman filter for wireless network synchronization (D. Pallier, V. Le Cam, A. Bouche, S. Pillement, Q. Zhang, L. Mevel), In International Workshop on Structure Health Monitoring, 2019. [bib]
[2018] High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques (T.T. Nguyen, S. Pillement, M. Thevenin, A. Mouraud, G. Corre, O. Pasquier), In Reconfigurable Architecture Workshop, 2018. [bib]
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