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Full list of publications. Sorted by year.

See also:

My Google scholar profil for a comprehensive survey of my publications.
The DBLP Computer Science Bibliography
ORCID ID

Recent Publications

Articles

2021
[2021]	0-1 ILP-based Run-Time Hierarchical Energy Optimization for Heterogeneous Cluster-based multi/many-core Systems (Yang, S., Le Nours, S., Mendez-Real, M. and Pillement, S.), In Journal of System Architecture, 2021. [bibtex] [doi]
[2021]	A Measurement-based Message-level Timing Prediction Approach for Data-Dependent SDFGs on Tile-based Heterogeneous MPSoCs (Stemmer, R., Vu, H., Le Nours, S., Gruttner, K., Pillement, S. and Nebel, W.), In Applied Sciences (Switzerland), 2021. [bibtex]
[2021]	Energy-efficient GPS synchronization for wireless nodes (D. Pallier, Le Cam, V. and S. Pillement), In IEEE Sensors Journal, volume 21, 2021. [bibtex] [doi]
2017
[2017]	FTUC: A Flooding Tree Uneven Clustering protocol for wireless sensor network (H. Wei, S. Pillement and D. Xu), In SENSORS, volume 17, 2017. [bibtex] [doi]
[2017]	Cooperative Spectrum Sensing With Small Sample Size in CWSNs (S. Men, P. Chargé and S. Pillement), In Wireless Personal Communications, volume 96, 2017. [bibtex] [doi]

Conference Papers

2023
[2023]	Securing a RISC-V architecture: A dynamic approach (Pillement, S., Mendez-Real, M., Pottier, J., Nieddu, T., Le Gall, B., Faucou, S., Béchennec, J.L., Briday, M., Girbal, S., Le Rhun, J., Gilles, O., Gracia Pérez, D., Sintzoff, A. and Coulon, J.R.), In Design Automation and Test in Europe, 2023. [bibtex]
[2023]	Timing and Power Modeling of Neural Networks Deployed onMulti-Core platforms (Dariol, Q., Le Nours, S., Pillement, S., Stemmer, R., Helms, D. and Grüttner, K.), 2023. [bibtex]
[2023]	Fast-Yet-Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms (Dariol, Q., Le Nours, S., Helms, D., Stemmer, R., Pillement, S and Grüttner, K.), In Rapid Simulation and Performance Evaluation for Design Optimization: Methods and Tools (RAPIDO), 2023. [bibtex]
[2023]	Formal Verification of Divider Circuits by Hardware Reduction (Cieselski, M., Yasin, A., Su, T. and Pillement, S.), In Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, 2023. [bibtex]
2022
[2022]	Gestion de systèmes embarqués à base de FPGA orienté qualité d'expérience avec réutilisation de modules reconfigurables (Duhamel, A., Pillement, S. and Kouki, W.), 2022. [bibtex]
[2022]	QoS aware design-time/run-time manager for FPGA-based embedded systems (Duhamel, A and Pillement, S.), In DASIP, 2022. [bibtex]
[2022]	A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks onMulti-Core Platforms (Q. Dariol, S. Le Nours, S. Pillement, R. Stemmer, D. Helms and K. Grüttner), In SAMOS, 2022. [bibtex]
2021
[2021]	Experimental Evaluation of Statistical Model Checking Methods for Probabilistic Timing Analysis of Multiprocessor Systems (Vu, H., Le Nours, S. and Pillement, S.), In Euromicro Digital System Design (DSD), 2021. [bibtex]
[2021]	A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoC (Vu, H., Le Nours, S., Pillement, S., Stemmer, R. and Grüttner, K.), In ASP-DAC, 2021. [bibtex]
2020
[2020]	SPEAR: Hardware-based Implicit Rewriting for Square-root Verification (Yasin, A., Su, T., Pillement, S. and Cieselski, M.), In Design Automation and Test in Europe, 2020. [bibtex]
[2020]	Formal Verification of Constrained Arithmetic Circuits Using Computer Algebraic Approach (Su, T., Yasin, A., Pillement, S. and Cieselski, M.), In Symposium on VLSI (ISVLSI), 2020. [bibtex]
[2020]	Towards Probabilistic Timing Analysis for SDFGs on Tile Based Heterogeneous MPSoCs (Stemmer, R., Vu, H., Pillement, S., Le Nours, S. and Grüttner, K.), In Embedded Real Time Systems (ERTS), 2020. [bibtex]
[2020]	Towards Malicious Exploitation of Energy Management Mechanisms (Noubir, S., Real, M. M. and Pillement, S.), In Design Automation and Test in Europe, 2020. [bibtex]
2019
[2019]	Functional Verification of Hardware Dividers using Algebraic Model (Yasin, A., Su, T., Pillement, S. and Cieselski, M.), In Conference on Very Large Scale Integration (VLSI-SoC), 2019. [bibtex]
[2019]	Formal Verification of Integer Dividers: Division by a Constant (A. Yasin, T. Su, S. Pillement and M. Cieselski), In ISVLSI Symposium, 2019. [bibtex]
[2019]	Mapping and Frequency Joint Optimization for Energy Efficient Execution of Multiple Applications on Multicore Systems (Yang S., Real, M. M., Le Nours, S. and Pillement, S.), In DASIP, 2019. [bibtex]
[2019]	System-Level Modeling and Simulation of MPSoC Run-Time Management using Execution Traces Analysis (S. Yang, S. Le Nours, M. Mendez Real and S. Pillement), In Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIX), 2019. [bibtex]
[2019]	Experimental Evaluation of Probabilistic Execution-Time Modeling and Analysis Methods for SDF Applications on MPSoCs. (R. Stemmer, H.D. Vu, K. Grüttner, S. Le Nours, W. Nebel and S. Pillement), In Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIX), 2019. [bibtex]
2018
[2018]	Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection (D. Solet, M. Briday, J.L. Bechennec, S. Faucou and S. Pillement), In European Dependable Computing Conference, 2018. [bibtex]
[2018]	HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems (D. Solet, M. Briday, J.L. Bechennec, S. Faucou and S. Pillement), In NASA/ESA Conference on Adaptive Hardware and Systems, 2018. [bibtex]
[2018]	FPGA Side Channel Attacks without Physical Access (C. Ramesh, S. Patil, S.Nishok Dhanuskodi, G. Provelengios, S. Pillement, D. Holcomb and R. Tessier), In International Symposium on Field-Programmable Custom Computing Machines, 2018. [bibtex]
2017
[2017]	Model-driven reliability evaluation for MPSoC design (TT Nguyen, A. Mouraud, M. Thévenin, G. Corre, O. Pasquier and S. Pillement), In DASIP, 2017. [bibtex]

Workshop Papers

2019
[2019]	Offset Tracking of sensor clock using Kalman filter for wireless network synchronization (D. Pallier, V. Le Cam, A. Bouche, S. Pillement, Q. Zhang and L. Mevel), In International Workshop on Structure Health Monitoring, 2019. [bibtex]
2018
[2018]	High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques (T.T. Nguyen, S. Pillement, M. Thevenin, A. Mouraud, G. Corre and O. Pasquier), In Reconfigurable Architecture Workshop, 2018. [bibtex]