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Sébastien Pillement Homepage

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Professor in Computer Engineering, Evolving within the SysCom research team (IETR Lab)


  • Wish you a Merry Christmas and an happy new year. See you in 2022
  • The team has one open PhD thesis position in NoC design for AI accelerators, in collaboration with the CEA. More information here.
  • In the framework of the ANR PRCE SecV project a master internship position is open. More information here.
  • Welcome to Fatima El Bouchiki who start a PhD in collaboration with IRISA in the framework of the NOP project
  • The Nantes node of FIT IoT-Lab is available for public through the federation.
  • A short presentation of our research activities can be found here .

Topics of interests

My research activities focus on the design and the management of Dynamically Reconfigurable Architectures (DRA). More precisely I investigate the following areas:
  • New approaches in dynamically reconfigurable architecture (HW and SW point of view),
  • Design of efficient and flexible interconnections,
  • Dedicated embedded operating system for DRA,
  • Fault-tolerant systems and reliability in embedded systems.
  • Hardware security in embedded systems.

Available Positions (Master, PhD, Post-doc, and Engineer)

If you are interested in any of these positions, or if you want more information, please contact me by email.

Post-doctoral position:


Master position:

Engineer internship:

Where and how to contact me

My email: Sebastien.Pillement AT

Polytech - Université de Nantes
IETR Nantes - SysCom Team
rue Christian Pauc
44000 Nantes - FRANCE
Tel : +33 (0)2-40-68-30-64
Bureau : C116

UPARC Download

The "UPaRC|Ultra-Fast Power-aware Reconfiguration Controller" VHDL code can be downloaded here.


The french embedded systems community propose a classification of top ranked publications for the SoC-SiP domain. The result can be found here