The Ultra-fast Power-aware Reconfiguration controller (UPaRC) boost the reconfiguration throughput up to 1.433 GB/s. UPaRC can not only enhance the system performance, but also auto-adapt to various performance and consumption conditions. This could enlarge the range of applications and optimize for each selected application during run-time.
UPaRC is build around a DMA and a pipeline controller for configuration bitstream pre-fetch.

An investigation of reconfiguration bandwidths at different frequencies and with different bitstream sizes were experimentally quantified. The results shows an improvement by a factor up to 100 vs the classical Xilinx hw_ICAP [1], and a factor 2 vs the most advanced controller FARM [3].

UPaRC is a hardware intellectual property (IP) core dedicated to Xilinx FPGAs. This IP provides very high speed reconfiguration rate including power consumption consideration. This software was tested on Virtex 5 and Virtex 6 architectures, using the Xilinx ISE 12.4. The name provided here may change depending on the user change and the software version. Rapid ICAP and bram socket IPs are mandatory to instanciate the reconfiguration controller (UReC). Reclogen is an IP to manage reconfiguration clock frequency and is used to face power considerations.
The provided archive contains the vhdl code of the proposed cores and a light documentation for installation and use process.