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Sébastien Pillement Research

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Full list of publications

Publications of Pillement [rss]
2016
[142] Hardware Runtime Verification of Embedded Software in SoPC (D. Solet, and J.L. Bechennec, M. Briday, S. Faucou, S. Pillement), In International Symposium on Industrial Embedded Systems, 2016. [bib]
[141] Implémentation matérielle de moniteurs sur un SoPC (D. Solet, S. Pillement, M. Briday, J.L. Bechennec, S. Faucou), 2016. (hal-01307981) (Colloque du GDR SoC-SiP) [bib]
[140] Cooperative Spectrum Sensing With Small Sample Size in CWSNs (S. Men, P. Chargé, S. Pillement), In Wireless Personal Communications, 2016. [bib]
[139] Outillage pour la modélisation, la vérification et la génération d'applications temporisées et embarquées (P.-E. Hladik, S. Dal Zilio, O. Pasquier, S. Pillement, B. Berthomieu), 2016. (AFADL) [bib]
[138] A method for determinig by optimization a multi-core architecture (R. Brillu, F. Lemonnier, P. Millet, S. Pillement), 2016. [bib]
2015
[137] Conception de systèmes cyber-physiques tolérants aux fautes (S. Pillement), 2015. (FETCH) [bib]
[136] A Robust and Energy Efficient Cooperative Spectrum Sensing Scheme in Cognitive Wireless Sensor Networks (S. Men, P. Chargé, S. Pillement), In International Journal of Network Protocols and Algorithms, volume 7, 2015. [bib]
[135] An Improved D-S Theory Cooperative Spectrum Sensing Algorithm in Cognitive Wireless Sensor Networks (S. Men, P. Chargé, S. Pillement), Technical report, The third Sino-French Workshop on Information and Communication Technologies (SIFWICT 2015), 2015. [bib]
[134] A Robust Cooperative Spectrum Sensing Method against Faulty Nodes in CWSNs (S. Men, P. Chargé, S. Pillement), In ICC - Workshop on Advances in Software Defined and Context Aware Cognitive Networks, 2015. [bib]
[133] Procédé de détermination par optimisation d'une architecture multi-cøe urs (R. Brillu, F. Lemonnier, P. Millet, S. Pillement), 2015. [bib]
[132] Fast Prototyping of a New Reconfigurable Architecture : Toward Tailored Space FPGA (C. Basha, S. Pillement, L. lagadec, A. Tisserand), In Conférence d'informatique en Parallélisme, Architecture et Système, ComPAS, 2015. [bib]
[131] Fault-aware Configurable Logic Block for Reliable Reconfigurable FPGAs (C. Basha, S. Pillement, S. Piestrak), In International Symposium on Circuits and Systems, 2015. [bib]
2014
[130] Method and device for programming a FPGA (O. Sentieys, A. Courtay, C. Huriaux, S. Pillement), 2014. [bib]
[129] Design of the Coarse-Grained Reconfigurable Architecture DART with On-Line Error Detection (S. Jafri, S. Piestrak, O. Sentieys, S. Pillement), In Journal on Microprocessors and Microsystems, volume 38, 2014. [bib] [doi]
[128] OCEAN, a flexible adaptive Network-On-Chip for dynamic applications (L. Devaux, S. Pillement), In Journal on Microprocessors and Microsystems, volume 38, 2014. [bib] [doi]
[127] Cluster based MPSoC architecture: An on-chip message passing implementation (R. Brillu, S. Pillement, F. Lemonnier, P. Millet), In Design Automation for Embedded Systems, volume 17, 2014. [bib] [doi]
[126] FlexTiles: A globally homogeneous but locally heterogeneous manycore architecture (R. Brillu, S. Pillement, A. Abdellah, F. Lemonnier, P. Millet), In Workshop on Rapid Simulation & Performance Evaluation: Methods and Tools of the HiPEAC conference, 2014. [bib]
[125] Towards a design space exploration tool for MPSoC platforms designs: a case study (R. Brillu, S. Pillement, F. Lemonnier, P. Millet, E. Lenormand, M. Bernot, F. Falzon), In Euromicro Conference on Parallel, Distributed, and Network-Based Processing, 2014. [bib]
[124] Designing with Uncertainty - Opportunities & Challenges workshop (C. Basha, S. Pillement), 2014. (PANDA workshop) [bib]
[123] Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs (C. Basha, S. Pillement, S. Piestrak), In Applied Reconfigurable Computing, 2014. [bib]
[122] New Reconfigurable Fault Tolerant FPGA Architecture : A Design for Mission Critical Applications (C. Basha, S. Pillement, L. lagadec), In Workshop on Reconfigurable Computing of the HiPEAC conference, 2014. [bib]
2013
[121] Mécanismes de la tolérance aux fautes dans les systèmes embarqués (S. Pillement), Technical report, Salon ENOVA, 2013. [bib]
[120] Architecture Reconfigurable dynamiquement Tolérante aux fautes (S. Pillement), 2013. (Journée "Utilisation de codes détecteurs et/ou correcteurs d'erreurs pour fiabiliser les traitements numériques au sein de circuits non fiables" du GDR ISIS) [bib]
[119] Low Overhead Fault-Tolerance Technique for Dynamically Reconfigurable Softcore Processor (M. Pham, S. Pillement, S. Piestrak), In IEEE Transactions on Computers, IEEE Computer Society, volume 62, 2013. [bib] [doi]
[118] Ordonnancement spatio-temporel pour une architecture 3D composée d'une couche multiprocesseur et d'une couche ressource reconfigurables (Q. Khuat, and Q. Le, D. Chillet, S. Pillement), In Conférence d'informatique en Parallélisme, Architecture et Système, ComPAS, 2013. [bib]
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