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Sébastien Pillement Homepage

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Professor in Computer Engineering, Evolving within the SysCom research team (IETR Lab)


  • The ANR PRCE SecV project has been selected for funding. More info soon.
  • The Cominlabs project NOP in collaboration with LS2N and IRISA has been selected. More info soon.
  • The Nantes node of FIT IoT-Lab will be sson available for public. News in october 2021
  • Welcome to Andrea Pinna who will start a 12 months leave in the team
  • Welcome to Sylvain Takougang which start a PhD in collaboration with LiP6 and UToronto
  • July 2020: The IETR becomes the "Institut d'Electronique and Technologies du numéRique"
  • A short presentation of our research activities can be found here .

Topics of interests

My research activities focus on the design and the management of Dynamically Reconfigurable Architectures (DRA). More precisely I investigate the following areas:
  • New approaches in dynamically reconfigurable architecture (HW and SW point of view),
  • Design of efficient and flexible interconnections,
  • Dedicated embedded operating system for DRA,
  • Fault-tolerant systems and reliability in embedded systems.
  • Hardware security in embedded systems.

Available Positions (Master, PhD, Post-doc, and Engineer)

If you are interested in any of these positions, or if you want more information, please contact me by email.

Post-doctoral position:


Master position:

Engineer internship:

Where and how to contact me

My email: Sebastien.Pillement AT

Polytech - Université de Nantes
IETR Nantes - SysCom Team
rue Christian Pauc
44000 Nantes - FRANCE
Tel : +33 (0)2-40-68-30-64
Bureau : C116

UPARC Download

The "UPaRC|Ultra-Fast Power-aware Reconfiguration Controller" VHDL code can be downloaded here.


The french embedded systems community propose a classification of top ranked publications for the SoC-SiP domain. The result can be found here