Accès direct au contenu

 

Sébastien Pillement Homepage

A- A+ Aa

Professor in Computer Engineering, Evolving within the SysCom research team (IETR Lab)

News

  • march 2020: The paper "Towards Malicious Exploitation of Energy Management Mechanisms" will be presented at DATE 2020 conference .
  • march 2020: The paper "SPEAR: Hardware-based Implicit Rewriting for Square-root Verification " will be presented at DATE 2020 conference .
  • Welcome to Xian Liu and Alexis Duhamel who start a PhD thesis in the team
  • The RFI project SEROIF in collaboration with Tec Monterey (Mexico) has been selected. More info soon.
  • The RFI project ConFienSe in collaboration with LARIS has been selected. More info soon.
  • A short presentation of our research activities can be found here .

Topics of interests

My research activities focus on the design and the management of Dynamically Reconfigurable Architectures (DRA). More precisely I investigate the following areas:
  • New approaches in dynamically reconfigurable architecture (HW and SW point of view),
  • Design of efficient and flexible interconnections,
  • Dedicated embedded operating system for DRA,
  • Fault-tolerant systems and reliability in embedded systems.
  • Hardware security in embedded systems.

Available Positions (Master, PhD, Post-doc, and Engineer)

If you are interested in any of these positions, or if you want more information, please contact me by email.

Post-doctoral position:

PhD:

Master position:

Engineer internship:

Where and how to contact me

My email: Sebastien.Pillement AT univ-nantes.fr

Polytech - Université de Nantes
IETR Nantes - SysCom Team
rue Christian Pauc
44000 Nantes - FRANCE
Tel : +33 (0)2-40-68-30-64
Bureau : C116

UPARC Download

The "UPaRC|Ultra-Fast Power-aware Reconfiguration Controller" VHDL code can be downloaded here.

Focus

The french embedded systems community propose a classification of top ranked publications for the SoC-SiP domain. The result can be found here