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Sébastien Pillement Research

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Publications of Pillement - page 4 [rss]
[67] Flot d'ordonnancement pour architecture reconfigurable (A. Eiche, D. Chillet, S. Pillement, O. Sentieys), In Symposium en Architecture de machines (SympA), 2009. [bib]
[66] DRAFT: Flexible Interconnection Network for Dynamically Reconfigurable Architectures (L. Devaux, S. Ben Sassi, S. Pillement, D. Chillet, D. Demigny), In IEEE International Conference on Field-Programmable Technology (FPT'), 2009. [bib]
[65] Réseau d'interconnexion flexible pour architecture reconfigurable dynamiquement et partiellement (L. Devaux, S. Ben Sassi, S. Pillement, D. Chillet, D. Demigny), In Symposium en Architecture de machines (SympA), 2009. [bib]
[64] Flexible communication support for dynamically reconfigurable FPGAs (L. Devaux, D. Chillet, S. Pillement, D. Demigny), In Southern Programmable Logic Conference (SPL'09), 2009. [bib]
[63] Ordonnancement de tâches par réseaux de neurones pour architectures de SoC hétérogènes (D. Chillet, S. Pillement, O. Sentieys), Chapter in Traitement du Signal, Lavoisier, volume 26, 2009. [bib]
[62] OveRSoC : Rapport Scientifique (M. Benkhelifa, D. Chillet, S. Garcia, B. Granado, E. Huck, L. Kessal, B. Miramond, S. Pillement, J.-C. Prévotet, F. Verdier, S. Viateur), Technical report, Consortium OverSoC, 2009. [bib]
2008
[61] A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources (J.C. Prevotet, A. Benkhelifa, B. Granado, E. Huck, B. Miramond, F. Verdier, D. Chillet, S. Pillement), In International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2008. [bib]
[60] A New Approach of Coding to Improve Speed and Noise Tolerance of On-Chip Busses (S. Pillement, JM. Philippe, O. Sentieys), In International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2008. [bib] [doi]
[59] DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency (S. Pillement, O. Sentieys, R. David), In EURASIP Journal on Embedded Systems (JES), volume 1, 2008. [bib] [pdf] [doi]
[58] Plate-forme de calcul générique pour véhicule intelligent (M. Pham, S. Pillement), Technical report, Projet Serhaiv, 2008. [bib]
[57] Efficient Dynamic Reconfiguration for Multi-context Embedded FPGA (J. Lallet, S. Pillement, O. Sentieys), In Symposium on Integrated circuits and system design (SBCCI), ACM, 2008. [bib] [doi]
[56] Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable SoC (D. Chillet, S. Pillement, O. Sentieys), In Conference on Design and Architectures for Signal and Image Processing (DASIP), 2008. [bib]
2007
[55] Placement dynamique de tâches sur ARD : Un survol (S. Pillement), 2007. (Séminaire au LRTS, Laval, Québec) [bib]
[54] TDSI et reconfigurables : Etude d'implémentations (S. Pillement, D. Menard, O. Sentieys), 2007. (Journée du GDR ISIS) [bib]
[53] Architectures reconfigurable faible consommation -- réalité ou prospective ? (S. Pillement, R. David), Chapter in Technique et Science Informatiques, numéro spécial SoC, Lavoisier, volume 26, 2007. [bib]
[52] Modeling of Interconnection Networks in Massively Parallel Processor Architectures (A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, J. Lallet, O. Sentieys, S. Pillement), In International Conference on Architecture of Computing Systems (ARCS), volume 4415, 2007. [bib]
[51] Co-Design of Massively Parallel Embedded Processor Architectures (R. Keryell, B. Pottier, O. Sentieys, S. Pillement), Technical report, P2R CoMAP, 2007. [bib]
[50] Vers une implémentation matérielle d'un réseau de neurones pour le service d'ordonnancement des tâches au sein d'un SoC (D. Chillet, S. Pillement, O. Sentieys), In Colloque sur le Traitement du Signal et des Images (GRETSI), 2007. [bib]
[49] A Neural Network Model for Real-Time Scheduling on Heteregeneous SoC Architectures (D. Chillet, S. Pillement, O. Sentieys), In International Joint Conference on Neural Networks (IJCNN), 2007. [bib]
[48] Hardware Task Scheduling for Heterogeneous SoC Architectures (I. Benkermi, D. Chillet, S. Pillement, O. Sentieys), In European Signal Processing Conference (EUSIPCO), 2007. [bib]
2006
[47] Vers un language de description d'architectures reconfigurables (S. Pillement, J. Lallet, O. Sentieys), 2006. (Séminaire du GDR SoC-SiP) [bib]
[46] Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects (J. M. Philippe, S. Pillement, O. Sentieys), In IEEE International Symposium on Quality Electronic Design (ISQED), 2006. [bib]
[45] An Energy-Efficient Ternary Interconnection Link for Asynchronous Systems (J. M. Philippe, E. Kinvi-Boh, S. Pillement, O. Sentieys), In IEEE International Symposium on Circuits and Systems (ISCAS), 2006. [bib]
[44] Clear stream towards dynamically reconfigurable systems on chip (N. Abel, L. Kessal, S. Pillement, D. Demigny), In Workshop on Reconfigurable Communication-Centric SoCs (ReCoSoC), 2006. [bib]
2005
[43] Exploring RTOS issues with a high-level model of a reconfigurable SoC platform (François Verdier, J.C. Prévotet, A. Benkhelifa, D. Chillet, S. Pillement), In Workshop on Reconfigurable Communication-Centric SoCs (ReCoSoC), 2005. [bib]
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