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Sébastien Pillement Research

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Full list of publications

Publications of Pillement - page 5 [rss]
[42] Low Power Electronics Design (R. David, S. Pillement, O. Sentieys), Chapter in Energy-Efficient Reconfigurable Processors, CRC Press, 2005. [bib]
[41] Modélisation niveau système de SoC reconfigurables (I. Benkermi, A. Benkhelifa, D. Chillet, S. Pillement, J.C. Prevotet, F. Verdier), In Symposium en Architecture de machines (SympA), 2005. [bib]
[40] A Low-Power And High-Speed Quaternary Interconnection Link Using Efficient Converters (J. M. Philippe, S. Pillement, O. Sentieys), In IEEE International Symposium on Circuits and Systems (ISCAS), 2005. [bib]
[39] Du microprocesseur au circuit FPGA : une analyse sous l'angle de la reconfiguration (R. David, D. Lavenier, S. Pillement), Chapter in Technique et Science Informatiques, Hermes Science Publications, volume 24, 2005. [bib]
[38] System-Level Modelling for Reconfigurable SoCs (I. Benkermi, A. Benkhelifa, D. Chillet, S. Pillement, J.C. Prévotet, F. Verdier), In Conference on Design of Circuits and Integrated Systems (DCIS), 2005. [bib]
2004
[37] EPML POMARD Thème 2 : Architectures (S. Pillement), 2004. (Séminaire du RTP SoC) [bib]
[36] Acceleration of a VLIW Processor With Dynamic Reconfiguration (F. Ben Abdallah, S. Pillement, O. Sentieys, A. Bouallegue), In IEEE International Conference on Microelectronics (ICM), 2004. [bib]
2003
[35] Papier invité : Architectures reconfigurables : opportunités pour la faible consommation (S. Pillement, R. David, O. Sentieys), In Colloque Faible Tension Faible Consommation (FTFC'03), 2003. [bib]
[34] Design and Implementation of WCDMA Platforms: Challenges and Trade-offs (D. Menard, M. Guitton, S. Pillement, O. Sentieys), In International Signal Processing Conference, 2003. [bib]
[33] …valuation comparative de plates-formes reconfigurables et programmables pour les télécommunications de 3ème génération (D. Menard, M. Guitton, R. David, S. Pillement, O. Sentieys), In Colloque sur le Traitement du Signal et des Images (GRETSI), 2003. [bib]
[32] Application des réseaux de neurones á l'ordonnancement de tâches temps réel sur une architecture multiprocesseurs hétérogènes (I. Benkermi, S. Pillement, O. Sentieys), In Symposium en Architecture de machines (SympA), 2003. [bib]
2002
[31] DART : a dynamically reconfigurable architecture dealing with future mobile telecommunications constraints (R. David, D. Chillet, S. Pillement, O. Sentieys), In IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2002. [bib]
[30] A High-Performance dynamically reconfigurable embedded architecture (R. David, D. Chillet, S. Pillement, O. Sentieys), In Sophia Antipolis Forum on Microelectronics (SAME), 2002. [bib]
[29] Mapping Future Generation Mobile Telecommunication Applications on a Dynamically Reconfigurable Architecture (R. David, D. Chillet, S. Pillement, O. Sentieys), In 27th IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2002. [bib]
[28] Flot de Conception pour Plateforme Reconfigurable (R. David, D. Chillet, S. Pillement, O. Sentieys), 2002. (Acte du colloque de CAO de circuits intégrés et systèmes) [bib]
[27] Behavioral IP Specification and Integration Framework for High-Level Design Reuse (O. Sentieys, S. Pillement, D. Chillet), In IEEE International Symposium on Quality Electronic Design (ISQED), 2002. [bib]
[26] A Virtual Component for Motion Estimation Algorithm (D. Chillet, S. Pillement, O. Sentieys), In Engineering of Reconfigurable Systems & Algorithms (ERSA), 2002. [bib]
[25] Vers une approche unifiée pour la conception globale des terminaux de télécommunications (D. Chillet, S. Pillement, O. Sentieys, al.), In Journées Francophones sur l'Adéquation Algorithme Architecture, 2002. [bib]
[24] A Compilation Framework for a Dynamically Reconfigurable Architecture (R. David, D. Chillet, S. Pillement, O. Sentieys), In International Conference on Field Programmable Logic and Applications (FPL), Springer Verlag, volume 2438, 2002. [bib]
[23] SOC Design Methodologies (R. David, D. Chillet, S. Pillement, O. Sentieys), Chapter in A Dynamically Reconfigurable Architecture for Low-Power Multimedia terminals, Kluwer Academic Publishers, volume 218, 2002. [bib]
2001
[22] Design and Synthesis of Behavioral Level Virtual Components (S. Pillement, O. Sentieys, D. Chillet, E. Casseau, P. Coussy, E.Martin, G. Savaton, S. Roux), In International Conference on Very Large Scale Integration (VLSI-SOC), 2001. [bib]
[21] Vers la définition de composants virtuels au niveau algorithmique (S. Pillement, O. Sentieys, D. Chillet), In Colloque sur le Traitement du Signal et des Images (GRETSI), 2001. [bib]
[20] A Dynamically Reconfigurable Architecture for Low-Power Multimedia terminals (R. David, D. Chillet, S. Pillement, O. Sentieys), In International Conference on Very Large Scale Integration (VLSI-SOC), 2001. [bib]
[19] Architectures Enfouies Reconfigurables Dynamiquement (R. David, S. Pillement, O. Sentieys, D. Chillet), In Symposium en Architecture de machines (SympA), 2001. [bib]
[18] Sous projet 2 : Méthode de spécification des applications (S. Pillement, O. Sentieys), 2001. [bib]
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