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Sébastien Pillement Research

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Publications of Pillement - page 3 [rss]
[92] Error Recovery Technique for Coarse-Grained Reconfigurable Architectures (M. Azeem, S. Piestrak, O. Sentieys, S. Pillement), In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011. [bib]
[91] A design methodology for specification and performances evaluation of Network On Chip (D. Adrouche, R. Sadoun, S. Pillement), In IEEE International Workshop on Reliability Aware System Design and Test, 2011. [bib]
2010
[90] Spatio-temporal Coding to Improve Speed and Noise Tolerance of On-chip Interconnect (S. Pillement, JM. Philippe, O. Sentieys), In MicroElectronics Journal, Elsevier, volume 41, 2010. [bib] [pdf] [doi]
[89] On designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication (S. Piestrak, S. Pillement, O. Sentieys), In IEEE Transactions on Circuits and Systems, part II, volume 57, 2010. [bib] [pdf] [doi]
[88] Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication" (S. Piestrak, S. Pillement, O. Sentieys), In IEEE Communications Letters, volume 14, 2010. [bib] [pdf] [doi]
[87] Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoC (M. Pham, S. Pillement, D. Demigny), In International Conference on Field Programmable Logic and Applications (FPL 10), 2010. [bib]
[86] Dynamic NOC-based MPSoC with Fault-Tolerance Support (M. Pham, L. Devaux, S. Pillement), In DAC Workshop on "Diagnostic Services in Network-on-Chips (DSNoC)", 2010. [bib]
[85] FT-DyMPSoC: Analytical Model for Fault-Tolerant Dynamic MPSoC (M. Pham, S. Pillement, D. Demigny), In IEEE Symposium on Field-Programmable Custom Computing Machines, 2010. [bib]
[84] Design of a Fault-Tolerant Coarse-Grained Reconfigurable Architecture: A Case Study (S. Jafri, S. Piestrak, O. Sentieys, S. Pillement), In IEEE International Symposium on Quality Electronic Design (ISQED), 2010. [bib]
[83] Calcul reconfigurable dynamiquement : du transistor au système (Sébastien Pillement), PhD thesis, Habilitation á Diriger des Recherches, University of Rennes 1, 2010. [bib]
[82] Task placement for dynamic and partial reconfigurable architecture (A. Eiche, D. Chillet, S. Pillement, O. Sentieys), In Conference on Design and Architectures for Signal and Image Processing (DASIP), 2010. [bib]
[81] R2NoC : dynamically Reconfigurable Routers for flexible Networks on Chip (L. Devaux, S. Pillement, D. Chillet, D. Demigny), In International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2010. [bib]
[80] OS Services for Reconfigurable System-on-Chip Communications (L. Devaux, S. Pillement, D. Chillet, D. Demigny), In Design of Circuits and Integrated Systems (DCIS'10), 2010. [bib] [pdf]
[79] Mesh and Fat-Tree comparison for dynamically reconfigurable applications (L. Devaux, S. Pillement, D. Chillet, D. Demigny), In Workshop on Reconfigurable Communication-Centric SoCs (ReCoSoC), 2010. [bib]
[78] Flexible interconnection network for dynamically and partially reconfigurable architectures (L. Devaux, S. Ben Sassi, S. Pillement, D. Chillet, D. Demigny), In International Journal on Reconfigurable Computing, volume 2010, 2010. [bib] [pdf] [doi]
2009
[77] High-Level Exploration for Dynamic Reconfiguration Management (S. Pillement, D. Chillet, Y. Oliva, J. C. Prevotet), In Engineering of Reconfigurable Systems & Algorithms (ERSA), CSREA Press, 2009. [bib]
[76] High-level Model of Dynamically Reconfigurable Architectures (S. Pillement, D. Chillet), In Conference on Design and Architectures for Signal and Image Processing (DASIP), 2009. [bib]
[75] A Fault-Tolerant Layer For Dynamically Reconfigurable Multi-Processor System-On-Chip (M. Pham, S. Pillement, D. Demigny), In International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2009. [bib]
[74] Reconfigurable ECU Communications in Autosar Environment (M. Pham, S. Pillement, D. Demigny), In 9th International Conference on ITS Telecommunications, 2009. [bib]
[73] Exploration for Dynamic Reconfiguration Management (Y Oliva-Venegas, J-C. Prevotet, F. Nouvel, S. Pillement, D. Chillet), In Sophia Antipolis MicroElectronics Forum, SAME 2009, 2009. [bib]
[72] OveRSoC : a Framework for the Exploration of RTOS for RSoC Platforms (B. Miramond, E. Huck, F. Verdier, A. Benkhelifa, B. Granado, T. Lefebvre, M. Aïchouch, J.C. Prevotet, Y. Oliva, D. Chillet, S. Pillement), In International Journal of Reconfigurable Computing, volume 2009, 2009. [bib] [pdf] [doi]
[71] Plate-forme de Conception d'Architectures Reconfigurables Dynamiquement pour le Domaine du TSI (J. Lallet, S. Pillement, O. Sentieys), In Colloque sur le Traitement du Signal et des Images (GRETSI), 2009. [bib]
[70] Efficient and Flexible Dynamic Reconfiguration for Multi-Context Architectures (Julien Lallet, Sébastien Pillement, Olivier Sentieys), In Journal of Integrated Circuits and Systems, volume 4, 2009. [bib] [pdf]
[69] xMAML: a Modeling Language for Dynamically Reconfigurable Architectures (Julien Lallet, Sébastien Pillement, Olivier Sentieys), In Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), 2009. [bib]
[68] Flot d'Ordonnancement Temps Réel d'un Ensemble de Tâches Matérielles pour Architecture Reconfigurable (A. Eiche, D. Chillet, S. Pillement, O. Sentieys), 2009. (Workshop GDR SoCSiP) [bib]
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