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Full list of publications

Book Chapters

2011
[2011]	Reconfigurable ECU communications in AUTOSAR Environment (Pham, M. and Pillement, S.), Chapter in Ingénieurs de l'Automobile, SIA, volume 813, 2011. [bibtex]
[2011]	Vehicular Technologies (Nouvel, F., Tanguy, P., Pillement, S. and Pham, M.), Chapter in Experiments of in-vehicle power line Communications (Miguel Almeida, ed.), Intech, 2011. [bibtex]
[2011]	RANN: A Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable System-on-Chip (D. Chillet, S. Pillement and O. Sentieys), Chapter in (G. Gogniat, D. Milojevic, A. Morawiec, A. T. Erdogan, eds.), Springer Verlag, volume 73, 2011. [bibtex]
2009
[2009]	Ordonnancement de tâches par réseaux de neurones pour architectures de SoC hétérogènes (D. Chillet, S. Pillement and O. Sentieys), Chapter in Traitement du Signal, Lavoisier, volume 26, 2009. [bibtex]
2007
[2007]	Architectures reconfigurable faible consommation – réalité ou prospective ? (S. Pillement and R. David), Chapter in Technique et Science Informatiques, numéro spécial SoC, Lavoisier, volume 26, 2007. [bibtex]
2005
[2005]	Energy-Efficient Reconfigurable Processors (R. David, S. Pillement and O. Sentieys), Chapter in , CRC Press, 2005. [bibtex]
[2005]	Du microprocesseur au circuit FPGA : une analyse sous l'angle de la reconfiguration (R. David, D. Lavenier and S. Pillement), Chapter in Technique et Science Informatiques, Hermes Science Publications, volume 24, 2005. [bibtex]
2002
[2002]	A Dynamically Reconfigurable Architecture for Low-Power Multimedia terminals (R. David, D. Chillet, S. Pillement and O. Sentieys), Chapter in , Kluwer Academic Publishers, volume 218, 2002. [bibtex]
1999
[1999]	VLSI: Systems on a Chip (S. Raimbault, G. Sassatelli, G. Cambon, M. Robert, S. Pillement and L. Torres), Chapter in Embedded systems design and verification : Reuse oriented prototyping methodologies, Kluwer Academic Publishers, volume 162, 1999. [bibtex]
1998
[1998]	CODESIGN conception conjointe logiciel-matériel (S. Pillement, L. Torres, M. Robert and G.Cambon), Chapter in Aide á la validation de systèmes logiciels/matériels, Eyrolles, 1998. [bibtex]
1997
[1997]	Models in System Design (S. Pillement, L. Torres, M. Robert and G. Cambon), Chapter in LIRMM : prototyping platform for hardware / software codesign, Kluwer Academic Publishers, volume 9, 1997. [bibtex]

Articles

2021
[2021]	0-1 ILP-based Run-Time Hierarchical Energy Optimization for Heterogeneous Cluster-based multi/many-core Systems (Yang, S., Le Nours, S., Mendez-Real, M. and Pillement, S.), In Journal of System Architecture, 2021. [bibtex] [doi]
[2021]	A Measurement-based Message-level Timing Prediction Approach for Data-Dependent SDFGs on Tile-based Heterogeneous MPSoCs (Stemmer, R., Vu, H., Le Nours, S., Grüttner, K., Pillement, S. and Nebel, W.), In Applied Sciences (Switzerland), 2021. [bibtex]
[2021]	Energy-efficient GPS synchronization for wireless nodes (D. Pallier, Le Cam, V. and S. Pillement), In IEEE Sensors Journal, volume 21, 2021. [bibtex] [doi]
2017
[2017]	FTUC: A Flooding Tree Uneven Clustering protocol for wireless sensor network (H. Wei, S. Pillement and D. Xu), In SENSORS, volume 17, 2017. [bibtex] [doi]
[2017]	Cooperative Spectrum Sensing With Small Sample Size in CWSNs (S. Men, P. Chargé and S. Pillement), In Wireless Personal Communications, volume 96, 2017. [bibtex] [doi]
2015
[2015]	A Robust and Energy Efficient Cooperative Spectrum Sensing Scheme in Cognitive Wireless Sensor Networks (S. Men, P. Chargé and S. Pillement), In International Journal of Network Protocols and Algorithms, volume 7, 2015. [bibtex] [doi]
2014
[2014]	Design of the Coarse-Grained Reconfigurable Architecture DART with On-Line Error Detection (S. Jafri, S. Piestrak, O. Sentieys and S. Pillement), In Journal on Microprocessors and Microsystems, volume 38, 2014. [bibtex] [doi]
[2014]	OCEAN, a flexible adaptive Network-On-Chip for dynamic applications (L. Devaux and S. Pillement), In Journal on Microprocessors and Microsystems, volume 38, 2014. [bibtex] [doi]
[2014]	Cluster based MPSoC architecture: An on-chip message passing implementation (R. Brillu, S. Pillement, F. Lemonnier and P. Millet), In Design Automation for Embedded Systems, volume 17, 2014. [bibtex] [doi]
2013
[2013]	Low Overhead Fault-Tolerance Technique for Dynamically Reconfigurable Softcore Processor (Pham, M., Pillement, S. and Piestrak, S.), In IEEE Transactions on Computers, IEEE Computer Society, volume 62, 2013. [bibtex] [doi]
2011
[2011]	Real-Time Scheduling on Heterogeneous System-on-Chip Architectures Using an Optimized Artificial Neural Networks (Chillet,, D., Eiche, A., Pillement,, S. and Sentieys,, O.), In Journal of Systems Architecture, volume 57, 2011. [bibtex] [url] [doi]
2010
[2010]	Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication" (S. Piestrak, S. Pillement and O. Sentieys), In IEEE Communications Letters, volume 14, 2010. [bibtex] [url] [doi]
[2010]	Spatio-temporal Coding to Improve Speed and Noise Tolerance of On-chip Interconnect (S. Pillement, JM. Philippe and O. Sentieys), In MicroElectronics Journal, Elsevier, volume 41, 2010. [bibtex] [url] [doi]
[2010]	On designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication (S. Piestrak, S. Pillement and O. Sentieys), In IEEE Transactions on Circuits and Systems, part II, volume 57, 2010. [bibtex] [url] [doi]
[2010]	Flexible interconnection network for dynamically and partially reconfigurable architectures (L. Devaux, S. Ben Sassi, S. Pillement, D. Chillet and D. Demigny), In International Journal on Reconfigurable Computing, volume 2010, 2010. [bibtex] [html] [doi]
2009
[2009]	OveRSoC : a Framework for the Exploration of RTOS for RSoC Platforms (B. Miramond, E. Huck, F. Verdier, A. Benkhelifa, B. Granado, T. Lefebvre, M. Aïchouch, J.C. Prevotet, Y. Oliva, D. Chillet and S. Pillement), In International Journal of Reconfigurable Computing, volume 2009, 2009. [bibtex] [html] [doi]
[2009]	Efficient and Flexible Dynamic Reconfiguration for Multi-Context Architectures (Julien Lallet, Sébastien Pillement and Olivier Sentieys), In Journal of Integrated Circuits and Systems, volume 4, 2009. [bibtex] [pdf]
2008
[2008]	DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency (S. Pillement, O. Sentieys and R. David), In EURASIP Journal on Embedded Systems (JES), volume 1, 2008. [bibtex] [html] [doi]

Conference Papers

2023
[2023]	Securing a RISC-V architecture: A dynamic approach (Pillement, S., Mendez-Real, M., Pottier, J., Nieddu, T., Le Gall, B., Faucou, S., Béchennec, J.L., Briday, M., Girbal, S., Le Rhun, J., Gilles, O., Gracia Pérez, D., Sintzoff, A. and Coulon, J.R.), In Design Automation and Test in Europe, 2023. [bibtex]
[2023]	Processeur RISC-V enrichi avec une unité de microdécodage dynamique (Nieddu, T., Le Gall, B. and Pillement, S.), 2023. [bibtex]
[2023]	Timing and Power Modeling of Neural Networks Deployed onMulti-Core platforms (Dariol, Q., Le Nours, S., Pillement, S., Stemmer, R., Helms, D. and Grüttner, K.), 2023. [bibtex]
[2023]	Fast-Yet-Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms (Dariol, Q., Le Nours, S., Helms, D., Stemmer, R., Pillement, S and Grüttner, K.), In Rapid Simulation and Performance Evaluation for Design Optimization: Methods and Tools (RAPIDO), 2023. [bibtex]
[2023]	Formal Verification of Divider Circuits by Hardware Reduction (Cieselski, M., Yasin, A., Su, T. and Pillement, S.), In Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, 2023. [bibtex]
2022
[2022]	The french RISC-V contest: an Analysis (Quévremont, J., Pillement, S. and Benoit, P.), 2022. [bibtex]
[2022]	Gestion de systèmes embarqués à base de FPGA orienté qualité d'expérience avec réutilisation de modules reconfigurables (Duhamel, A., Pillement, S. and Kouki, W.), 2022. [bibtex]
[2022]	QoS aware design-time/run-time manager for FPGA-based embedded systems (Duhamel, A. and Pillement, S.), In Conference on Design and Architectures for Signal and Image Processing (DASIP), 2022. [bibtex]
[2022]	A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-Core Platforms (Q. Dariol, S. Le Nours, S. Pillement, R. Stemmer, D. Helms and K. Grüttner), In Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2022. [bibtex]
2021
[2021]	Experimental Evaluation of Statistical Model Checking Methods for Probabilistic Timing Analysis of Multiprocessor Systems (Vu, H., Le Nours, S. and Pillement, S.), In Euromicro Digital System Design (DSD), 2021. [bibtex]
[2021]	A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoC (Vu, H., Le Nours, S., Pillement, S., Stemmer, R. and Grüttner, K.), In ASP-DAC, 2021. [bibtex]
2020
[2020]	SPEAR: Hardware-based Implicit Rewriting for Square-root Verification (Yasin, A., Su, T., Pillement, S. and Cieselski, M.), In Design Automation and Test in Europe, 2020. [bibtex]
[2020]	Formal Verification of Constrained Arithmetic Circuits Using Computer Algebraic Approach (Su, T., Yasin, A., Pillement, S. and Cieselski, M.), In Symposium on VLSI (ISVLSI), 2020. [bibtex]
[2020]	Towards Probabilistic Timing Analysis for SDFGs on Tile Based Heterogeneous MPSoCs (Stemmer, R., Vu, H., Pillement, S., Le Nours, S. and Grüttner, K.), In Embedded Real Time Systems (ERTS), 2020. [bibtex]
[2020]	Towards Malicious Exploitation of Energy Management Mechanisms (Noubir, S., Real, M. M. and Pillement, S.), In Design Automation and Test in Europe, 2020. [bibtex]
2019
[2019]	Functional Verification of Hardware Dividers using Algebraic Model (Yasin, A., Su, T., Pillement, S. and Cieselski, M.), In Conference on Very Large Scale Integration (VLSI-SoC), 2019. [bibtex]
[2019]	Formal Verification of Integer Dividers: Division by a Constant (A. Yasin, T. Su, S. Pillement and M. Cieselski), In ISVLSI Symposium, 2019. [bibtex]
[2019]	Mapping and Frequency Joint Optimization for Energy Efficient Execution of Multiple Applications on Multicore Systems (Yang, S., Real, M. M., Le Nours, S. and Pillement, S.), In Conference on Design and Architectures for Signal and Image Processing (DASIP), 2019. [bibtex]
[2019]	System-Level Modeling and Simulation of MPSoC Run-Time Management using Execution Traces Analysis (S. Yang, S. Le Nours, M. Mendez Real and S. Pillement), In Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2019. [bibtex]
[2019]	Experimental Evaluation of Probabilistic Execution-Time Modeling and Analysis Methods for SDF Applications on MPSoCs. (R. Stemmer, H.D. Vu, K. Grüttner, S. Le Nours, W. Nebel and S. Pillement), In Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2019. [bibtex]
2018
[2018]	Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection (D. Solet, M. Briday, J.L. Bechennec, S. Faucou and S. Pillement), In European Dependable Computing Conference, 2018. [bibtex]
[2018]	HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems (D. Solet, M. Briday, J.L. Bechennec, S. Faucou and S. Pillement), In NASA/ESA Conference on Adaptive Hardware and Systems, 2018. [bibtex]
[2018]	FPGA Side Channel Attacks without Physical Access (C. Ramesh, S. Patil, S.Nishok Dhanuskodi, G. Provelengios, S. Pillement, D. Holcomb and R. Tessier), In International Symposium on Field-Programmable Custom Computing Machines, 2018. [bibtex]
2017
[2017]	Model-driven reliability evaluation for MPSoC design (Nguyen, T., Mouraud, A., Thévenin, M., Corre, G., Pasquier, O. and Pillement, S.), In Conference on Design and Architectures for Signal and Image Processing (DASIP), 2017. [bibtex]
2016
[2016]	Hardware Runtime Verification of Embedded Software in SoPC (D. Solet, and J.L. Bechennec, M. Briday, S. Faucou and S. Pillement), In International Symposium on Industrial Embedded Systems, 2016. [bibtex]
2015
[2015]	Fast Prototyping of a New Reconfigurable Architecture : Toward Tailored Space FPGA (C. Basha, S. Pillement, L. lagadec and A. Tisserand), 2015. [bibtex]
[2015]	Fault-aware Configurable Logic Block for Reliable Reconfigurable FPGAs (Basha, C., Pillement, S. and Piestrak, S.), In International Symposium on Circuits and Systems, 2015. [bibtex]
2014
[2014]	Towards a design space exploration tool for MPSoC platforms designs: a case study (R. Brillu, S. Pillement, F. Lemonnier, P. Millet, E. Lenormand, M. Bernot and F. Falzon), In Euromicro Conference on Parallel, Distributed, and Network-Based Processing, 2014. [bibtex]
[2014]	Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs (C. Basha, S. Pillement and S. Piestrak), In Applied Reconfigurable Computing, 2014. [bibtex]
2013
[2013]	Environnement de modélisation et de simulation d'architecture MPSoC : OVP une solution fiable et effective ? (R. Brillu, S. Pillement and F. Lemonnier), 2013. [bibtex]
[2013]	Ordonnancement spatio-temporel pour une architecture 3D composée d'une couche multiprocesseur et d'une couche ressource reconfigurables (Q. Khuat, and Q. Le, D. Chillet and S. Pillement), 2013. [bibtex]
[2013]	Algorithm-Architecture Adequacy, an application to the phase diversity algorithm (R. Brillu, S. Pillement, F. Lemonnier, P. Millet, M. Bernot and F. Falzon), 2013. [bibtex]
2012
[2012]	Spatio-Temporal Scheduling for 3D Reconfigurable & Multiprocessor Architecture (Q. Khuat, Q. Le, D. Chillet and S. Pillement), In International Design and Test Symposium, IDT 2012, 2012. [bibtex]
[2012]	Gradient - An Adaptive Fault-tolerant Routing Algorithm for 2D Mesh Network-on-Chips (Pratomo, I. and Pillement, S.), In Conference on Design and Architectures for Signal and Image Processing (DASIP), 2012. [bibtex]
[2012]	Towards future adaptive multiprocessor systems-on-chip: an innovative approach for flexible architectures (Lemonnier, F., Millet, P., Marchesan Almeida, G., Hubner, M., Becker, J., Pillement, S., Sentieys, O., Koedam, M., Sinha, S., Goossens, K., Piguet, C., Morgan, M. and Lemaire, R.), In Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2012. [bibtex]
[2012]	Impact of Design Parameters on Performance of Adaptive Network-on-Chips (I. Pratomo and Pillement, S.), In High Performance Computing and Simulation (HPCS), 2012. [bibtex]
[2012]	UPaRC - Ultra-Fast Power-aware Reconfiguration Controller (Pham, M., Bonamy, R., Pillement, S. and Chillet, D.), In Design and Test in Europe (DATE), 2012. [bibtex]
2011
[2011]	Hardware OS Communication Service and Dynamic Memory Management for RSoCs (S. Narayanan, D. Chillet, S. Pillement and I. Sourdis), In International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2011. [bibtex]
[2011]	A Framework for the Design of Reconfigurable Fault Tolerant Architectures (Pham, M., Pillement, S., Le Nours, S. and Pasquier, O.), In Conference on Design and Architectures for Signal and Image Processing (DASIP), 2011. [bibtex]
[2011]	Parallel Evaluation of Hopfield Neural Networks (Eiche, A., Chillet, D., Pillement, S. and Sentieys, O.), In Conference on Neural Computation Theory and Applications, 2011. [bibtex]
[2011]	Exploitation du concept de tolérance aux fautes des réseaux de neurones pour la résolution de problèmes d'optimisation (Chillet, D., Eiche, A., Pillement, S. and Sentieys, O.), 2011. [bibtex]
[2011]	Communication Service for hardware tasks executed on dynamic and partial reconfigurable resource (S. Narayanan, L. Devaux, D. Chillet, S. Pillement and I. Sourdis), In Conference on Very Large Scale Integration (VLSI-SoC), 2011. [bibtex]
[2011]	Implémentation matérielle d'un réseau de neurones pour l'ordonnancement temporel de tâches sur architectures multi-processeur hétérogènes (A. Pasturel, A. Eiche, D. Chillet, S. Pillement and O. Sentieys), 2011. [bibtex]
[2011]	Modélisation et implémentation de calculateurs reconfigurables tolérants aux fautes et communications flexibles intra-véhicules (Pham, M., Pillement, S., Le Nours, S. and Pasquier, O.), 2011. [bibtex]
[2011]	Error Recovery Technique for Coarse-Grained Reconfigurable Architectures (M. Azeem, Piestrak, S., Sentieys, O. and Pillement, S.), In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011. [bibtex]
2010
[2010]	R2NoC : dynamically Reconfigurable Routers for flexible Networks on Chip (Devaux, L., Pillement, S., Chillet, D. and Demigny, D.), In International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2010. [bibtex]
[2010]	OS Services for Reconfigurable System-on-Chip Communications (L. Devaux, S. Pillement, D. Chillet and D. Demigny), In Design of Circuits and Integrated Systems (DCIS'10), 2010. [bibtex] [url]
[2010]	Task placement for dynamic and partial reconfigurable architecture (A. Eiche, D. Chillet, S. Pillement and O. Sentieys), In Conference on Design and Architectures for Signal and Image Processing (DASIP), 2010. [bibtex]
[2010]	FT-DyMPSoC: Analytical Model for Fault-Tolerant Dynamic MPSoC (M. Pham, S. Pillement and D. Demigny), In IEEE Symposium on Field-Programmable Custom Computing Machines, 2010. [bibtex]
[2010]	Design of a Fault-Tolerant Coarse-Grained Reconfigurable Architecture: A Case Study (S. Jafri, S. Piestrak, O. Sentieys and S. Pillement), In IEEE International Symposium on Quality Electronic Design (ISQED), 2010. [bibtex]
[2010]	Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoC (M. Pham, S. Pillement and D. Demigny), In International Conference on Field Programmable Logic and Applications (FPL 10), 2010. [bibtex]
2009
[2009]	DRAFT: Flexible Interconnection Network for Dynamically Reconfigurable Architectures (L. Devaux, S. Ben Sassi, S. Pillement, D. Chillet and D. Demigny), In IEEE International Conference on Field-Programmable Technology (FPT'), 2009. [bibtex]
[2009]	A Fault-Tolerant Layer For Dynamically Reconfigurable Multi-Processor System-On-Chip (M. Pham, S. Pillement and D. Demigny), In International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2009. [bibtex]
[2009]	Reconfigurable ECU Communications in Autosar Environment (M. Pham, S. Pillement and D. Demigny), In 9th International Conference on ITS Telecommunications, 2009. [bibtex]
[2009]	Exploration for Dynamic Reconfiguration Management (Oliva-Venegas,, Y, Prevotet,, J-C., Nouvel,,F., Pillement,, S. and Chillet,, D.), In Sophia Antipolis MicroElectronics Forum, SAME 2009, 2009. [bibtex]
[2009]	Réseau d'interconnexion flexible pour architecture reconfigurable dynamiquement et partiellement (L. Devaux, S. Ben Sassi, S. Pillement, D. Chillet and D. Demigny), 2009. [bibtex]
[2009]	Flot d'ordonnancement pour architecture reconfigurable (Eiche, A., Chillet, D., Pillement, S. and Sentieys, O.), 2009. [bibtex]
[2009]	Plate-forme de Conception d'Architectures Reconfigurables Dynamiquement pour le Domaine du TSI (J. Lallet, S. Pillement and O. Sentieys), 2009. [bibtex]
[2009]	xMAML: a Modeling Language for Dynamically Reconfigurable Architectures (Julien Lallet, Sébastien Pillement and Olivier Sentieys), In Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), 2009. [bibtex]
[2009]	High-level Model of Dynamically Reconfigurable Architectures (Pillement, S. and Chillet, D.), In Conference on Design and Architectures for Signal and Image Processing (DASIP), 2009. [bibtex]
[2009]	High-Level Exploration for Dynamic Reconfiguration Management (Pillement,, S., Chillet,, D., Oliva,, Y. and Prevotet,, J. C.), In Engineering of Reconfigurable Systems & Algorithms (ERSA), CSREA Press, 2009. [bibtex]
[2009]	Flexible communication support for dynamically reconfigurable FPGAs (L. Devaux, D. Chillet, S. Pillement and D. Demigny), In Southern Programmable Logic Conference (SPL'09), 2009. [bibtex]
2008
[2008]	A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources (J.C. Prevotet, A. Benkhelifa, B. Granado, E. Huck, B. Miramond, F. Verdier, D. Chillet and S. Pillement), In International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2008. [bibtex]
[2008]	Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable SoC (D. Chillet, S. Pillement and O. Sentieys), In Conference on Design and Architectures for Signal and Image Processing (DASIP), 2008. [bibtex]
[2008]	A New Approach of Coding to Improve Speed and Noise Tolerance of On-Chip Busses (S. Pillement, JM. Philippe and O. Sentieys), In International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2008. [bibtex] [doi]
[2008]	Efficient Dynamic Reconfiguration for Multi-context Embedded FPGA (J. Lallet, S. Pillement and O. Sentieys), In Symposium on Integrated circuits and system design (SBCCI), ACM, 2008. [bibtex] [doi]
2007
[2007]	Hardware Task Scheduling for Heterogeneous SoC Architectures (I. Benkermi, D. Chillet, S. Pillement and O. Sentieys), In European Signal Processing Conference (EUSIPCO), 2007. [bibtex]
[2007]	Vers une implémentation matérielle d'un réseau de neurones pour le service d'ordonnancement des tâches au sein d'un SoC (D. Chillet, S. Pillement and O. Sentieys), 2007. [bibtex]
[2007]	A Neural Network Model for Real-Time Scheduling on Heteregeneous SoC Architectures (D. Chillet, S. Pillement and O. Sentieys), In International Joint Conference on Neural Networks (IJCNN), 2007. [bibtex]
[2007]	Modeling of Interconnection Networks in Massively Parallel Processor Architectures (A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, J. Lallet, O. Sentieys and S. Pillement), In International Conference on Architecture of Computing Systems (ARCS), volume 4415, 2007. [bibtex]
2006
[2006]	An Energy-Efficient Ternary Interconnection Link for Asynchronous Systems (J. M. Philippe, E. Kinvi-Boh, S. Pillement and O. Sentieys), In IEEE International Symposium on Circuits and Systems (ISCAS), 2006. [bibtex]
[2006]	Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects (J. M. Philippe, S. Pillement and O. Sentieys), In IEEE International Symposium on Quality Electronic Design (ISQED), 2006. [bibtex]
2005
[2005]	System-Level Modelling for Reconfigurable SoCs (I. Benkermi, A. Benkhelifa, D. Chillet, S. Pillement, J.C. Prévotet and F. Verdier), In Conference on Design of Circuits and Integrated Systems (DCIS), 2005. [bibtex]
[2005]	A Low-Power And High-Speed Quaternary Interconnection Link Using Efficient Converters (J. M. Philippe, S. Pillement and O. Sentieys), In IEEE International Symposium on Circuits and Systems (ISCAS), 2005. [bibtex]
[2005]	Modélisation niveau système de SoC reconfigurables (I. Benkermi, A. Benkhelifa, D. Chillet, S. Pillement, J.C. Prevotet and F. Verdier), 2005. [bibtex]
2004
[2004]	Acceleration of a VLIW Processor With Dynamic Reconfiguration (F. Ben Abdallah, S. Pillement, O. Sentieys and A. Bouallegue), In IEEE International Conference on Microelectronics (ICM), 2004. [bibtex]
2003
[2003]	Application des réseaux de neurones á l'ordonnancement de tâches temps réel sur une architecture multiprocesseurs hétérogènes (I. Benkermi, S. Pillement and O. Sentieys), 2003. [bibtex]
[2003]	Papier invité : Architectures reconfigurables : opportunités pour la faible consommation (S. Pillement, R. David and O. Sentieys), 2003. [bibtex]
[2003]	Evaluation comparative de plates-formes reconfigurables et programmables pour les télécommunications de 3ème génération (D. Menard, M. Guitton, R. David, S. Pillement and O. Sentieys), 2003. [bibtex]
[2003]	Design and Implementation of WCDMA Platforms: Challenges and Trade-offs (D. Menard, M. Guitton, S. Pillement and O. Sentieys), In International Signal Processing Conference, 2003. [bibtex]
2002
[2002]	Vers une approche unifiée pour la conception globale des terminaux de télécommunications (D. Chillet, S. Pillement, O. Sentieys and al.), 2002. [bibtex]
[2002]	A High-Performance dynamically reconfigurable embedded architecture (R. David, D. Chillet, S. Pillement and O. Sentieys), In Sophia Antipolis Forum on Microelectronics (SAME), 2002. [bibtex]
[2002]	A Compilation Framework for a Dynamically Reconfigurable Architecture (R. David, D. Chillet, S. Pillement and O. Sentieys), In International Conference on Field Programmable Logic and Applications (FPL), Springer Verlag, volume 2438, 2002. [bibtex]
[2002]	A Virtual Component for Motion Estimation Algorithm (D. Chillet, S. Pillement and O. Sentieys), In Engineering of Reconfigurable Systems & Algorithms (ERSA), 2002. [bibtex]
[2002]	Mapping Future Generation Mobile Telecommunication Applications on a Dynamically Reconfigurable Architecture (R. David, D. Chillet, S. Pillement and O. Sentieys), In 27th IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2002. [bibtex]
[2002]	DART : a dynamically reconfigurable architecture dealing with future mobile telecommunications constraints (R. David, D. Chillet, S. Pillement and O. Sentieys), In IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2002. [bibtex]
[2002]	Behavioral IP Specification and Integration Framework for High-Level Design Reuse (O. Sentieys, S. Pillement and D. Chillet), In IEEE International Symposium on Quality Electronic Design (ISQED), 2002. [bibtex]
2001
[2001]	A Dynamically Reconfigurable Architecture for Low-Power Multimedia terminals (R. David, D. Chillet, S. Pillement and O. Sentieys), In International Conference on Very Large Scale Integration (VLSI-SOC), 2001. [bibtex]
[2001]	Design and Synthesis of Behavioral Level Virtual Components (S. Pillement, O. Sentieys, D. Chillet, E. Casseau, P. Coussy, E.Martin, G. Savaton and S. Roux), In International Conference on Very Large Scale Integration (VLSI-SOC), 2001. [bibtex]
[2001]	Vers la définition de composants virtuels au niveau algorithmique (S. Pillement, O. Sentieys and D. Chillet), 2001. [bibtex]
[2001]	Architectures Enfouies Reconfigurables Dynamiquement (R. David, S. Pillement, O. Sentieys and D. Chillet), 2001. [bibtex]
1999
[1999]	Embedded systems design and verification : Reuse oriented prototyping methodologies (S. Raimbault, G. Sassatelli, G. Cambon, M. Robert, S. Pillement and L. Torres), In International Conference on Very Large Scale Integration (VLSI-SOC), 1999. [bibtex]
1998
[1998]	Fast Prototyping for Hardware / Software Codesign (L. Torres, S. Pillement, S. Raimbault, L. Revelli, M. Robert and G. Cambon), In Sophia Antipolis Forum on Microelectronics (SAME), 1998. [bibtex]
1996
[1996]	A unified workbench for designing hardware / software systems (L. Maillet-Contoz, S. Pillement and J. Sallantin), In IFIP Working Conference on Logic and Architecture Synthesis, 1996. [bibtex]

Workshop Papers

2019
[2019]	Offset Tracking of sensor clock using Kalman filter for wireless network synchronization (D. Pallier, V. Le Cam, A. Bouche, S. Pillement, Q. Zhang and L. Mevel), In International Workshop on Structure Health Monitoring, 2019. [bibtex]
2018
[2018]	High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques (T.T. Nguyen, S. Pillement, M. Thevenin, A. Mouraud, G. Corre and O. Pasquier), In Reconfigurable Architecture Workshop, 2018. [bibtex]
2015
[2015]	A Robust Cooperative Spectrum Sensing Method against Faulty Nodes in CWSNs (S. Men, P. Chargé and S. Pillement), In ICC - Workshop on Advances in Software Defined and Context Aware Cognitive Networks, 2015. [bibtex]
2014
[2014]	FlexTiles: A globally homogeneous but locally heterogeneous manycore architecture (R. Brillu, S. Pillement, A. Abdellah, F. Lemonnier and P. Millet), In Workshop on Rapid Simulation & Performance Evaluation: Methods and Tools of the HiPEAC conference, 2014. [bibtex]
[2014]	New Reconfigurable Fault Tolerant FPGA Architecture : A Design for Mission Critical Applications (C. Basha, S. Pillement and L. lagadec), In Workshop on Reconfigurable Computing of the HiPEAC conference, 2014. [bibtex]
2013
[2013]	Accelerator Interface, a keystone for heterogenous "MPSoC" architectures (R. Brillu, S. Pillement and F. Lemonnier), In DATE Friday Workshop on Reconfigurable Computing V2.0: The Next Generation of Technology, Architectures and Design Tools, 2013. [bibtex]
2011
[2011]	Re2DA: Reliable and Reconfigurable Dynamic Architectures (Pham, M., Devaux, L. and Pillement, S.), In Workshop on Reconfigurable Communication-Centric SoCs (ReCoSoC), 2011. [bibtex]
[2011]	A design methodology for specification and performances evaluation of Network On Chip (Adrouche, D., Sadoun, R. and Pillement, S.), In IEEE International Workshop on Reliability Aware System Design and Test, 2011. [bibtex]
2010
[2010]	Dynamic NOC-based MPSoC with Fault-Tolerance Support (Pham, M., Devaux, L. and Pillement, S.), In DAC Workshop on "Diagnostic Services in Network-on-Chips (DSNoC)", 2010. [bibtex]
[2010]	Mesh and Fat-Tree comparison for dynamically reconfigurable applications (Devaux, L., Pillement, S., Chillet, D. and Demigny, D.), In Workshop on Reconfigurable Communication-Centric SoCs (ReCoSoC), 2010. [bibtex]
2006
[2006]	Clear stream towards dynamically reconfigurable systems on chip (N. Abel, L. Kessal, S. Pillement and D. Demigny), In Workshop on Reconfigurable Communication-Centric SoCs (ReCoSoC), 2006. [bibtex]
2005
[2005]	Exploring RTOS issues with a high-level model of a reconfigurable SoC platform (François Verdier, J.C. Prévotet, A. Benkhelifa, D. Chillet and S. Pillement), In Workshop on Reconfigurable Communication-Centric SoCs (ReCoSoC), 2005. [bibtex]
1999
[1999]	Fast Prototyping: A Case Study - The JPEG Compression Algorithm (S. Pillement, L. Torres, M. Robert and G. Cambon), In IEEE International Workshop on Rapid System Prototyping (RSP'99), 1999. [bibtex]
1996
[1996]	Concurrent design of hardware / software dedicated systems (S. Pillement, L. Torres, M. Robert and G. Cambon), In International Workshop on Field Programmable Logic and Applications (FPL), Springer Verlag, volume 1142, 1996. [bibtex]

Other Publications

2013
[2013]	Mécanismes de la tolérance aux fautes dans les systèmes embarqués (S. Pillement), Technical report, Salon ENOVA, 2013. [bibtex]
2012
[2012]	Les réseaux de capteurs totalement autonomes un état des lieux (S. Pillement and Y. Daubelcour), Technical report, Congrés Energies S2E2, 2012. [bibtex]
2010
[2010]	Calcul reconfigurable dynamiquement : du transistor au système (Sébastien Pillement), PhD thesis, Habilitation á Diriger des Recherches, University of Rennes 1, 2010. [bibtex]
2009
[2009]	OveRSoC : Rapport Scientifique (M. Benkhelifa, D. Chillet, S. Garcia, B. Granado, E. Huck, L. Kessal, B. Miramond, S. Pillement, J.-C. Prévotet, F. Verdier and S. Viateur), Technical report, Consortium OverSoC, 2009. [bibtex]
2008
[2008]	Plate-forme de calcul générique pour véhicule intelligent (Pham, M. and Pillement, S.), Technical report, Projet Serhaiv, 2008. [bibtex]
2007
[2007]	Co-Design of Massively Parallel Embedded Processor Architectures (R. Keryell, B. Pottier, O. Sentieys and Pillement, S.), Technical report, P2R CoMAP, 2007. [bibtex]
2001
[2001]	Sous projet 2 : Méthode de spécification des applications (S. Pillement and O. Sentieys), Technical report, LASTI, Université Rennes 1, 2001. [bibtex]
2000
[2000]	Sous projet 2 : Méthode de spécification des applications (S. Pillement and O. Sentieys), Technical report, LASTI, Université Rennes 1, 2000. [bibtex]
1998
[1998]	Méthodologies d'évaluation et de prototypage des systèmes numériques intégrés (Sébastien Pillement), PhD thesis, Université de Montpellier II, 1998. [bibtex]
1997
[1997]	Environnement d'aide á la conception concurrente de systèmes matériel/logiciel (G. Cambon, M. Robert, B. Rouzeyre, J. Sallantin, E. Lemoine, L. Torres, L. Maillet-Contoz, C. Vial and S. Pillement), Technical report, LIRMM, Université Montpellier II, 1997. [bibtex]
1996
[1996]	Environnement d'aide á la conception concurrente de systèmes dédiés logiciel/matériel (G. Cambon, L. Maillet-Contoz, S. Pillement, J. Sallantin, B. Rouzeyre, C. Vial and M. Robert), Technical report, LIRMM, Université Montpellier II, 1996. [bibtex]
1995
[1995]	CoDesign : Traduction du langage C en un langage de description matérielle (S. Pillement), Rapport de D.E.A. LIRMM-CNRS, Montpellier, 1995. [bibtex]