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Sébastien Pillement Research

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Publications of Pillement - page 2 [rss]
[117] Algorithm-Architecture Adequacy, an application to the phase diversity algorithm (R. Brillu, S. Pillement, F. Lemonnier, P. Millet, M. Bernot, F. Falzon), In GRETSI, 2013. [bib]
[116] Accelerator Interface, a keystone for heterogenous "MPSoC" architectures (R. Brillu, S. Pillement, F. Lemonnier), In DATE Friday Workshop on Reconfigurable Computing V2.0: The Next Generation of Technology, Architectures and Design Tools, 2013. [bib]
[115] Environnement de modélisation et de simulation d'architecture  MPSoC: OVP une solution fiable et effective ? (R. Brillu, S. Pillement, F. Lemonnier), In Conférence d'informatique en Parallélisme, Architecture et Système, ComPAS, 2013. [bib]
[114] An overview: Dynamically reconfigurable fault tolerant FPGA architectures (C. Basha, S. Pillement), 2013. (Séminaire du GDR SoC-SiP) [bib]
2012
[113] Gradient - An Adaptive Fault-tolerant Routing Algorithm for 2D Mesh Network-on-Chips (I. Pratomo, S. Pillement), In Conference on Design and Architectures for Signal and Image Processing (DASIP), 2012. [bib]
[112] Impact of Design Parameters on Performance of Adaptive Network-on-Chips (I. Pratomo, S. Pillement), In High Performance Computing and Simulation (HPCS), 2012. [bib]
[111] Les réseaux de capteurs totalement autonomes un état des lieux (S. Pillement, Y. Daubelcour), Technical report, Congrés Energies S2E2, 2012. [bib]
[110] ARDyT: Architecture Reconfigurable Dynamique Tolérante (S. Pillement, A. Tisserand, L. Lagadec, E. Fabianni, S. Piestrak), 2012. (Séminaire du GDR SoC-SiP) [bib]
[109] UPaRC - Ultra-Fast Power-aware Reconfiguration Controller (M. Pham, R. Bonamy, S. Pillement, D. Chillet), In Design and Test in Europe (DATE), 2012. [bib]
[108] Towards future adaptive multiprocessor systems-on-chip: an innovative approach for flexible architectures (F. Lemonnier, P. Millet, G. Marchesan Almeida, M. Hubner, J. Becker, S. Pillement, O. Sentieys, M. Koedam, S. Sinha, K. Goossens, C. Piguet, M. Morgan, R. Lemaire), In Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), 2012. [bib]
[107] Spatio-Temporal Scheduling for 3D Reconfigurable & Multiprocessor Architecture (Q. Khuat, Q. Le, D. Chillet, S. Pillement), In International Design and Test Symposium, IDT 2012, 2012. [bib]
[106] Spatio-Temporal Scheduling for 3D Reconfigurable & Multiprocessor Architectures (Q.and LE Q. Khuat, D. Chillet, S. Pillement), 2012. (Séminaire du GDR SoC-SiP) [bib]
2011
[105] A Framework for the Design of Reconfigurable Fault Tolerant Architectures (M. Pham, S. Pillement, S. Le Nours, O. Pasquier), In Conference on Design and Architectures for Signal and Image Processing (DASIP), 2011. [bib]
[104] Reconfigurable ECU communications in AUTOSAR Environment (M. Pham, S. Pillement), Chapter in Ingénieurs de l'Automobile, SIA, volume 813, 2011. [bib]
[103] Re2DA: Reliable and Reconfigurable Dynamic Architectures (M. Pham, L. Devaux, S. Pillement), In Workshop on Reconfigurable Communication-Centric SoCs (ReCoSoC), 2011. [bib]
[102] Modélisation et implémentation de calculateurs reconfigurables tolérants aux fautes et communications flexibles intra-véhicules (M. Pham, S. Pillement, S. Le Nours, O. Pasquier), In Symposium en Architecture de machines (SympA), 2011. [bib]
[101] Implémentation matérielle d'un réseau de neurones pour l'ordonnancement temporel de tâches sur architectures multi-processeur hétérogènes (A. Pasturel, A. Eiche, D. Chillet, S. Pillement, O. Sentieys), In Symposium en Architecture de machines (SympA), 2011. [bib]
[100] Architecture Embarquée Reconfigurable pour les communications Intra-véhicule (F. Nouvel, S. Philippe, S. Le Nours, S. Pillement), 2011. (Séminaire du GDR SoC-SiP) [bib]
[99] Vehicular Technologies (F. Nouvel, P. Tanguy, S. Pillement, M. Pham), Chapter in Experiments of in-vehicle power line Communications (Miguel Almeida, ed.), Intech, 2011. [bib]
[98] Hardware OS Communication Service and Dynamic Memory Management for RSoCs (S. Narayanan, D. Chillet, S. Pillement, I. Sourdis), In International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2011. [bib]
[97] Communication Service for hardware tasks executed on dynamic and partial reconfigurable resource (S. Narayanan, L. Devaux, D. Chillet, S. Pillement, I. Sourdis), In Conference on Very Large Scale Integration (VLSI-SoC), 2011. [bib]
[96] Parallel Evaluation of Hopfield Neural Networks (A. Eiche, D. Chillet, S. Pillement, O. Sentieys), In Conference on Neural Computation Theory and Applications, 2011. [bib]
[95] Exploitation du concept de tolérance aux fautes des réseaux de neurones pour la résolution de problèmes d'optimisation (D. Chillet, A. Eiche, S. Pillement, O. Sentieys), In GRETSI, 2011. [bib]
[94] Real-Time Scheduling on Heterogeneous System-on-Chip Architectures Using an Optimized Artificial Neural Networks (D. Chillet, A. Eiche, S. Pillement, O. Sentieys), In Journal of Systems Architecture, volume 57, 2011. [bib] [pdf] [doi]
[93] Algorithm-Architecture Matching for Signal and Image Processing (D. Chillet, S. Pillement, O. Sentieys), Chapter in RANN: A Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable System-on-Chip (D. Milojevic A. Morawiec G. Gogniat, A. T. Erdogan, eds.), Springer Verlag, volume 73, 2011. [bib]
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