Sébastien Pillement Homepage

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Professor in Computer Science, Evolving within the SCN research team (IETR Lab)

News

may 2013: the 12th is the extended deadline to submit paper to the DASIP conference
New available positions for internship (M2 level). More information here.
Ph.D. thesis of Ludovic Devaux "Flexible interconnection networks for dynamically reconfigurable architectures" is online.

Topics of interests

My research activities focus on the design and the management of Dynamically Reconfigurable Architectures (DRA). More precisely I investigate the following areas:

New approaches in dynamically reconfigurable architecture (HW point of view),
Design of efficient and flexible interconnections,
Dedicated embedded operating system for DRA,
Fault-tolerant systems.

Available Positions (Master, PhD, Post-doc, and Engineer)

If you are interested in any of these positions, or if you want more information, please contact me by email.

PhD:

[PhD] Cognitive Radio Sensor Networks: algorithms and architectures.
Supervisors: Sébastien Pillement and Pascal Chargé.
[PhD] Modèle et évaluation de méthodes de tolérances aux fautes dans un MPSOC hétérogène.
Supervisors: Sébastien Pillement and Olivier Pasquier.

Master position:

[Master] Energy Optimization of Network-On-Chip.
Supervisor: Sébastien Pillement.
[Master] Spatio-temporal scheduling for Dynamically Reconfigurable Architecture.
Supervisor: Sébastien Pillement.

Post-doctoral proposition:

Engineer internship:

[M2] Implementation of an hardware shared memory controller on a FPGA platform.
Supervisor: Sébastien Pillement, Romain Brillu.
[M2] Architecture reconfigurable pour la radio cognitive.
Supervisor: Sébastien Pillement, Pascal Chargé.

Where and how to contact me

My email: Sebastien.Pillement AT univ-nantes.fr

Polytech - Université de Nantes
IETR Nantes - SCN Team
rue Christian Pauc
44000 Nantes - FRANCE
Tel : +33 (0)2-40-68-30-64
Bureau : C116

Locations of visitors to this page

UPARC Download

The "UPaRC|Ultra-Fast Power-aware Reconfiguration Controller" VHDL code can be downloaded here.

Focus

extended deadline to submit paper to the DASIP conference.

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